1. Technical Field
This application relates to semiconductor memory devices, methods for controlling the same, and more particularly, to a semiconductor memory device and a method for controlling the same in which core control signals controlling read or write operations in semiconductor memory devices are enabled by one master signal.
2. Discussion of Related Art
In general, read and write operations in semiconductor memory devices are performed repeatedly. In the read operation, data in selected memory cells is read from the semiconductor memory device. In the write operation, external input data is stored in selected memory cells. Data input and output speed of semiconductor memory devices are key factors in determining the operational speed of a system that uses the semiconductor memory devices. Studies for improving the operational speed of semiconductor memory devices are ongoing. These studies have resulted in synchronous semiconductor memory devices (e.g., synchronous DRAMs; SDRAMs) having internal circuits synchronized with an external clock signal.
The synchronous semiconductor memory devices may be classified into single data rate synchronous memory devices (single data rate SDRAM; SDR SDRAM) and double data rate synchronous memory devices (double data rate SDRAM; DDR SDRAM). In SDR SDRAM, one set of data is input or output during one cycle of an external clock signal in response to a rising edge or a falling edge of the external clock signal. The DDR SDRAM, two sets of data are input or is output during one cycle of an external clock signal, one in response to a rising edge and one in response to a falling edge of the external clock signal. Consequently, DDR SDRAM may have a bandwidth that is two times greater than that of SDR SDRAM.
Several control signals are necessary for read and write operations in a semiconductor memory device. The semiconductor memory device is generally divided into a cell array area, a core area and a ferry area. The control signals are called core control signals since most of the control signals are generated in the core area.
FIG. 1 is a schematic block diagram of a data input and output path from a memory cell to input and output lines and associated circuits in a synchronous semiconductor memory device.
The data input and output path will be described with reference to FIG. 1. First, a data output path when data in a memory cell 10 is read in a read operation in a semiconductor memory device will be described.
The memory cell 10 is basically composed of one transistor and one capacitor. When a word line WL is selected and enabled in response to a row address, the transistor of the memory cell 10 is turned on and data in the capacitor is loaded on a bit line BL. The bit line BL forms a bit line pair with a complementary bit line BLB. The data on the bit line BL is sensed and amplified by a bit line sense amplifier 20. The amplified data on the pair of bit lines BL and BLB is loaded onto a pair of local input and output lines LIO and LIOB via transistors N1 and N2 responsive to a column select signal (CSL). For example, when the column select signal CSL for a specific column is enabled by a column address, data on bit line pair BL and BLB of the column is loaded onto the local input and output lines LIO and LIOB. The loaded data on the pair of the local input and output line LIO and LIOB is sensed and amplified by an input and output sense amplifier 40. Here, it is necessary to precharge the pair of the local input and output lines LIO and LIOB by means of the local input and output line precharge circuit 30 responsive to a local input and output line precharge signal LIOPRB before the column select signal CSL is enabled so that the sense amplifier 40 correctly senses data. The amplified data from the input and output sense amplifier 40 is loaded onto a pair of global input and output lines GIO and GIOB and is output outside the memory device. It is also necessary to precharge the global input and output lines GIO and GIOB prior to data transmission by means of the global input and output line precharge circuit 50 responsive to the global input and output line precharge signal GIOPRB.
A data input path, when data is written to a semiconductor memory cell, will be now described. When external data is input at the start of a write operation, the global input and output line driver circuit 60 sends external input data to the global input and output line pair GIO and GIOB. The global input and output line driver circuit 60 is enabled in response to a first data loading signal PDT. The data on the global input and output line pair GIO and GIOB is loaded to the local input and output line pair LIO and LIOB by a local input and output line driver circuit (not shown) responsive to a second data loading signal LGIOCON. The data on the local input and output line pair LIO and LIOB is loaded to the bit line pair BL and BLB by the transistors N1 and N2 responsive to the column select signal CSL and is stored in the memory cell 10.
As described above, to perform such read and write operations, the semiconductor memory device requires core control signals controlling the data input and output path.
Examples of the core control signals include a read/write identifying signal PWRD for identifying reading operation and writing operation, a first data loading signal PDT, a second data loading signal LGIOCON, input and output line precharge signals LIOPRB and GIOPRB for precharging input and output lines LIO, LIOB, GIO and GIOB, a sense amplifier enable signal LSAEN for enabling an input and output line sense amplifier, and a column select signal CSL for data transmission between a bit line pair BL and BLB and local input and output lines LIO and LIOB. These core control signals are generated in control signal generating circuits responsive to a master signal.
As used herein, a master signal is a signal for controlling generation of specific control signals. For example, a signal input to the column select signal CSL generating circuit in order to enable or disable the column select signal CSL is called a master signal for the column select signal CSL.
FIG. 2 is a timing diagram illustrating generation of the control signals.
As shown in FIG. 2, when an external clock signal CLK is applied, an internal clock signal PCLK is generated in synchronization with the external clock signal CLK. When read or write operation is initiated, a bank address BA for selecting one of memory banks constituting a cell array of a semiconductor memory device, and a first control signal PCLKCD as a delayed version of the internal clock signal PCLK are generated in response to a rising edge of the internal clock signal PCLK. Further, a second control signal PCSLD as a delayed version of the internal clock signal PCLK is generated in response to a rising edge of the next cycle of the internal clock signal. The column select signal CSL is enabled with a certain delay in response to a rising edge of the first control signal PCLKCD as a master signal and disabled with a certain delay in response to a rising edge of a second control signal PCSLD as a master signal. Core control signals IOPR and PWRD are enabled with a certain delay in response to a rising edge of the bank address signal BA as the master signal and disabled with a certain delay in response to a falling edge of the bank address signal BA. The core control signal IOPR is a complementary signal of input and output line precharge signals LIOPRB and GIOPRB. Other core control signals PDT, LGIOCON and LSAEN, which are not shown, either have a different master signal, or one of the above-described master signals.
As described above, the core control signals LIOPRB, GIOPRB, PWRD, PDT, LGIOCON and LSAEN have a different master signal from that for the column select signal CSL. Delay variation or power, voltage, and temperature (PVT) variation in core control signal generation circuits result in increased design time for the master signals. In addition, in the delay variation or the PVT variation makes it difficult to obtain the absolute margin between the signals.